A design of a general type of integrated circuit involves, for example, performing a time-wise analysis for a circuit and subsequently identifying a “critical path”, i.e., a “speed path”. Then, elements or components on this critical path are analyzed. Subsequently, a speed, power consumption, a chip size, etc are optimized for acquiring a desired operation speed of the circuit as a whole by conducting replacement with other cells or changing transistors to other types of transistors having different threshold values.
Further, after starting the manufacture also, in high-performance product which pursues high-speed performance, a threshold value is reduced by uniformly decreasing gate lengths of a chip as a whole or decreasing a concentration of a channel impurity in a way that changes a process recipe, thus taking measures for accelerating an operation speed of the chip.
The reduction in threshold value by uniformly decreasing the gate lengths or decreasing the concentration of the channel impurity is, however, a tradeoff with a rise in off-leak current. Hence, such a process change can not be made randomly, and improvement of the performance is limitative. Nevertheless, a background of implementing these measures leis in a request for manufacturing as many chips performing the high-speed operations as possible in a tradeoff relation between the speed and the power consumption.    [Patent document 1] Japanese Patent Laid-Open Publication No. 2009-86700    [Patent document 2] Japanese Patent Laid-Open Publication No. H10-256387    [Patent document 3] Japanese Patent Laid-Open Publication No. H05-326705    [Patent document 4] Japanese Patent Laid-Open Publication No. 2009-26829    [Patent document 5] Japanese Patent Laid-Open Publication No. 2008-250981